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| SC68C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs and 68 mode P interface Rev. 04 -- 20 January 2010 Product data sheet 1. General description The SC68C752B is a dual Universal Asynchronous Receiver/Transmitter (UART) with 64-byte FIFOs, automatic hardware/software flow control, and data rates up to 5 Mbit/s. The SC68C752B offers enhanced features. It has a Transmission Control Register (TCR) that stores receiver FIFO threshold levels to start/stop transmission during hardware and software flow control. With the FIFO Rdy register, the software gets the status of TXRDYn/RXRDYn for all four ports in one access. On-chip status registers provide the user with error indications, operational status, and modem interface control. System interrupts may be tailored to meet user requirements. An internal loopback capability allows on-board diagnostics. The UART transmits data, sent to it over the peripheral 8-bit bus, on the TXn signal and receives characters on the RXn signal. Characters can be programmed to be 5 bits, 6 bits, 7 bits, or 8 bits. The UART has a 64-byte receive FIFO and transmit FIFO and can be programmed to interrupt at different trigger levels. The UART generates its own desired baud rate based upon a programmable divisor and its input clock. It can transmit even, odd, or no parity and 1, 1.5, or 2 stop bits. The receiver can detect break, idle, or framing errors, FIFO overflow, and parity errors. The transmitter can detect FIFO underflow. The UART also contains a software interface for modem control operations, and has software flow control and hardware flow control capabilities. The SC68C752B is available in LQFP48 and HVQFN32 packages. 2. Features Dual channel with 68 mode (Motorola) P interface Up to 5 Mbit/s data rate 64-byte transmit FIFO 64-byte receive FIFO with error flags Programmable and selectable transmit and receive FIFO trigger levels for DMA and interrupt generation Software/hardware flow control Programmable Xon/Xoff characters Programmable auto-RTS and auto-CTS Optional data flow resume by Xon any character DMA signalling capability for both received and transmitted data Supports 5 V, 3.3 V and 2.5 V operation NXP Semiconductors SC68C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 5 V tolerant on input only pins1 Software selectable baud rate generator Prescaler provides additional divide-by-4 function Industrial temperature range (-40 C to +85 C) Fast data bus access time Programmable Sleep mode Programmable serial interface characteristics 5-bit, 6-bit, 7-bit, or 8-bit characters Even, odd, or no parity bit generation and detection 1, 1.5, or 2 stop bit generation False start bit detection Complete status reporting capabilities in both normal and Sleep mode Line break generation and detection Internal test and loopback capabilities Fully prioritized interrupt system controls Modem control functions (CTS, RTS, DSR, DTR, RI, and CD) 3. Ordering information Table 1. Ordering information Package Name SC68C752BIB48 LQFP48 SC68C752BIBS HVQFN32 Description plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm Version SOT313-2 Type number plastic thermal enhanced very thin quad flat package; SOT617-1 no leads; 32 terminals; body 5 x 5 x 0.85 mm 1. For data bus pins D7 to D0, see Table 25 "Limiting values". (c) NXP B.V. 2010. All rights reserved. SC68C752B_4 Product data sheet Rev. 04 -- 20 January 2010 2 of 48 NXP Semiconductors SC68C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 4. Block diagram SC68C752B TRANSMIT FIFO REGISTER D0 to D7 R/W RESET DATA BUS AND CONTROL LOGIC FLOW CONTROL LOGIC TRANSMIT SHIFT REGISTER TXA, TXB INTERCONNECT BUS LINES AND CONTROL SIGNALS RECEIVE FIFO REGISTER RECEIVE SHIFT REGISTER RXA, RXB A0 to A3 CS REGISTER SELECT LOGIC FLOW CONTROL LOGIC DTRS, DTRB RTSA, RTSB OPA, OPB MODEM CONTROL LOGIC IRQ TXRDYA, TXRDYB RXRDYA, RXRDYB INTERRUPT CONTROL LOGIC CLOCK AND BAUD RATE GENERATOR CTSA, CTSB RIA, RIB CDA, CDB DSRA, DSRB 002aab017 XTAL1 XTAL2 Fig 1. Block diagram of SC68C752B SC68C752B_4 (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 20 January 2010 3 of 48 NXP Semiconductors SC68C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 5. Pinning information 5.1 Pinning 43 TXRDYA 39 DSRA 38 CTSA 40 CDA 42 VCC 41 RIA D5 D6 D7 RXB RXA TXRDYB TXA TXB OPB 1 2 3 4 5 6 7 8 9 37 n.c. 36 RESET 35 DTRB 34 DTRA 33 RTSA 32 OPA 31 RXRDYA 30 IRQ 29 n.c. 28 A0 27 A1 26 A2 25 n.c. GND 24 002aab018 002aac014 46 D2 R/W 15 45 D1 CDB 16 SC68C752BIB48 CS 10 A3 11 n.c. 12 XTAL1 13 XTAL2 14 GND 17 RXRDYB 18 VCC 19 DSRB 20 RIB 21 RTSB 22 CTSB 23 Fig 2. Pin configuration for LQFP48 44 D0 48 D4 47 D3 32 D5 31 D4 30 D3 29 D2 28 D1 D6 D7 RXB RXA TXA TXB OPB CS 1 2 3 4 5 6 7 8 XTAL1 10 XTAL2 11 R/W 12 GND 13 n.c. 14 RTSB 15 CTSB 16 9 27 D0 terminal 1 index area 25 CTSA 24 RESET 23 RTSA 22 OPA 21 IRQ 20 n.c. 19 A0 18 A1 17 A2 SC68C752BIBS A3 Transparent top view Fig 3. Pin configuration for HVQFN32 SC68C752B_4 26 VCC (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 20 January 2010 4 of 48 NXP Semiconductors SC68C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 5.2 Pin description Table 2. Symbol A0 A1 A2 A3 CDA CDB Pin description Pin LQFP48 HVQFN32 28 27 26 11 40 16 19 18 17 9 I I I I I I Address 0 select bit. Internal registers address selection. Address 1 select bit. Internal registers address selection. Address 2 select bit. Internal registers address selection. Address 3. A3 is used to select Channel A or Channel B. A logic LOW selects Channel A, and a logic HIGH selects Channel B. (See Table 3.) Carrier Detect (active LOW). These inputs are associated with individual UART Channel A and Channel B. A logic LOW on these pins indicates that a carrier has been detected by the modem for that channel. The state of these inputs is reflected in the Modem Status Register (MSR). Chip Select (active LOW). This pin enables data transfers between the user CPU and the SC68C752B for the channel(s) addressed. Individual UART sections (A, B) are addressed by A3. See Table 3. Clear to Send (active LOW). These inputs are associated with individual UART Channel A and Channel B. A logic 0 (LOW) on the CTSn pins indicates the modem or data set is ready to accept transmit data from the SC68C752B. Status can be tested by reading MSR[4]. These pins only affect the transmit and receive operations when auto-CTS function is enabled via the Enhanced Feature Register EFR[7] for hardware flow control operation. Data bus (bidirectional). These pins are the 8-bit, 3-state data bus for transferring information to or from the controlling CPU. D0 is the least significant bit and the first data bit in a transmit or receive serial data stream. Type Description CS 10 8 I CTSA CTSB 38 23 25 15 I I D0 D1 D2 D3 D4 D5 D6 D7 DSRA DSRB 44 45 46 47 48 1 2 3 39 20 27 28 29 30 31 32 1 2 - I/O I/O I/O I/O I/O I/O I/O I/O I I Data Set Ready (active LOW). These inputs are associated with individual UART Channel A and Channel B. A logic 0 (LOW) on these pins indicates the modem or data set is powered-on and is ready for data exchange with the UART. The state of these inputs is reflected in the Modem Status Register (MSR). Data Terminal Ready (active LOW). These outputs are associated with individual UART Channel A and Channel B. A logic 0 (LOW) on these pins indicates that the SC68C752B is powered-on and ready. These pins can be controlled via the Modem Control Register. Writing a logic 1 to MCR[0] will set the DTRn output pin to logic 0 (LOW), enabling the modem. The output of these pins will be a logic 1 after writing a logic 0 to MCR[0], or after a reset. Signal and power ground. Interrupt Request. Interrupts from UART Channel A and Channel B are wire-ORed internally to function as a single IRQ interrupt. This pin transitions to a logic 0 (if enabled by the Interrupt Enable Register) whenever a UART channel(s) requires service. Individual channel interrupt status can be determined by addressing each channel through its associated internal register, using CS and A3. An external pull-up resistor must be connected between this pin and VCC. DTRA DTRB 34 35 - O O GND IRQ 17, 24 30 13[1] 21 I O SC68C752B_4 (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 20 January 2010 5 of 48 NXP Semiconductors SC68C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs Table 2. Symbol R/W Pin description ...continued Pin LQFP48 HVQFN32 15 12 I A logic LOW on this pin will transfer the contents of the data bus (D[7:0]) from an external CPU to an internal register that is defined by address bits A[2:0]. A logic HIGH on this pin will load the contents of an internal register defined by address bits A[2:0] on the SC68C752B data bus (D[7:0]) for access by an external CPU. not connected User defined outputs. This function is associated with individual Channel A and Channel B. The state of these pins is defined by the user through the software settings of MCR[3]. OPA/OPB is a logic 0 when MCR[3] is set to a logic 1. OPA/OPB is a logic 1 when MCR[3] is set to a logic 0. The output of these two pins is HIGH after reset. Reset (active LOW). This pin will reset the internal registers and all the outputs. The UART transmitter output and the receiver input will be disabled during reset time. RESET is an active LOW input. Ring Indicator (active LOW). These inputs are associated with individual UART Channel A and Channel B. A logic 0 on these pins indicates the modem has received a ringing signal from the telephone line. A LOW-to-HIGH transition on these input pins generates a modem status interrupt, if enabled. The state of these inputs is reflected in the Modem Status Register (MSR). Request to Send (active LOW). These outputs are associated with individual UART Channel A and Channel B. A logic 0 on the RTSn pin indicates the transmitter has data ready and waiting to send. Writing a logic 1 in the Modem Control Register MCR[1] will set this pin to a logic 0, indicating data is available. After a reset these pins are set to a logic 1. These pins only affect the transmit and receive operations when auto-RTS function is enabled via the Enhanced Feature Register (EFR[6]) for hardware flow control operation. Receive data input. These inputs are associated with individual serial channel data to the SC68C752B. During the local Loopback mode, these RXn input pins are disabled and transmit data is connected to the UART receive input internally. Receive Ready (active LOW). RXRDYA or RXRDYB goes LOW when the trigger level has been reached or the FIFO has at least one character. It goes HIGH when the receive FIFO is empty. Transmit data A, B. These outputs are associated with individual serial transmit channel data from the SC68C752B. During the local Loopback mode, the TXn output pin is disabled and transmit data is internally connected to the UART receive input. Transmit Ready (active LOW). TXRDYA or TXRDYB go LOW when there are at least a trigger level number of spaces available or when the FIFO is empty. It goes HIGH when the FIFO is full or not empty. Power supply input. Crystal or external clock input. Functions as a crystal input or as an external clock input. A crystal can be connected between XTAL1 and XTAL2 to form an internal oscillator circuit (see Figure 13). Alternatively, an external clock can be connected to this pin to provide custom data rates. Output of the crystal oscillator or buffered clock. (See also XTAL1.) XTAL2 is used as a crystal oscillator output or a buffered clock output. Type Description n.c. OPA OPB 12, 25, 29, 37 32 9 14, 20 22 7 O O RESET 36 24 I RIA RIB 41 21 - I I RTSA RTSB 33 22 23 16 O O RXA RXB RXRDYA RXRDYB TXA TXB 5 4 31 18 7 8 4 3 5 6 I I O O O O TXRDYA TXRDYB VCC XTAL1 43 6 19, 42 13 26 10 O O I I XTAL2 14 11 O SC68C752B_4 (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 20 January 2010 6 of 48 NXP Semiconductors SC68C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs [1] HVQFN32 package die supply ground is connected to both GND pin and exposed center pad. GND pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the PCB in the thermal pad region. Table 3. CS 1 0 0 Channel selection using CS pin A3 0 1 UART channel none channel A channel B 6. Functional description The UART will perform serial-to-parallel conversion on data characters received from peripheral devices or modems, and parallel-to-parallel conversion on data characters transmitted by the processor. The complete status of each channel of the SC68C752B UART can be read at any time during functional operation by the processor. The SC68C752B can be placed in an alternate mode (FIFO mode) relieving the processor of excessive software overhead by buffering received/transmitted characters. Both the receiver and transmitter FIFOs can store up to 64 bytes (including three additional bits of error status per byte for the receiver FIFO) and have selectable or programmable trigger levels. Primary outputs RXRDYn and TXRDYn allow signalling of DMA transfers. The SC68C752B has selectable hardware flow control and software flow control. Hardware flow control significantly reduces software overhead and increases system efficiency by automatically controlling serial data flow using the RTSn output and CTSn input signals. Software flow control automatically controls data flow by using programmable Xon/Xoff characters. The UART includes a programmable baud rate generator that can divide the timing reference clock input by a divisor between 1 and (216 - 1). 6.1 Trigger levels The SC68C752B provides independent selectable and programmable trigger levels for both receiver and transmitter DMA and interrupt generation. After reset, both transmitter and receiver FIFOs are disabled and so, in effect, the trigger level is the default value of one byte. The selectable trigger levels are available via the FCR. The programmable trigger levels are available via the Trigger Level Register (TLR). 6.2 Hardware flow control Hardware flow control is comprised of auto-CTS and auto-RTS. Auto-CTS and auto-RTS can be enabled/disabled independently by programming EFR[7:6]. With auto-CTS, CTSn must be active before the UART can transmit data. Auto-RTS only activates the RTSn output when there is enough room in the FIFO to receive data and de-activates the RTSn output when the receive FIFO is sufficiently full. The halt and resume trigger levels in the TCR determine the levels at which RTSn is activated/deactivated. SC68C752B_4 (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 20 January 2010 7 of 48 NXP Semiconductors SC68C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs If both auto-CTS and auto-RTS are enabled, when RTSn is connected to CTSn, data transmission does not occur unless the receive FIFO has empty space. Thus, overrun errors are eliminated during hardware flow control. If not enabled, overrun errors occur if the transmit data rate exceeds the receive FIFO servicing latency. UART 1 SERIAL TO PARALLEL RECEIVE FIFO FLOW CONTROL D7 to D0 PARALLEL TO SERIAL TRANSMIT FIFO FLOW CONTROL CTSn RTSn TXn RXn RTSn CTSn UART 2 PARALLEL TO SERIAL TRANSMIT FIFO FLOW CONTROL D7 to D0 SERIAL TO PARALLEL RECEIVE FIFO FLOW CONTROL 002aaf090 RXn TXn Fig 4. Auto flow control (auto-RTS and auto-CTS) example 6.2.1 Auto-RTS Auto-RTS data flow control originates in the receiver block (see Figure 1 "Block diagram of SC68C752B" on page 3). Figure 5 shows RTSn functional timing. The receiver FIFO trigger levels used in auto-RTS are stored in the TCR. RTSn is active if the receiver FIFO level is below the halt trigger level in TCR[3:0]. When the receiver FIFO halt trigger level is reached, RTSn is de-asserted. The sending device (for example, another UART) may send an additional byte after the trigger level is reached (assuming the sending UART has another byte to send) because it may not recognize the de-assertion of RTSn until it has begun sending the additional byte. RTSn is automatically reasserted once the receiver FIFO reaches the resume trigger level programmed via TCR[7:4]. This re-assertion allows the sending device to resume transmission. RXn Start byte N Stop Start byte N + 1 Stop Start RTSn R/W 1 2 N N+1 002aab086 N = receiver FIFO trigger level. The two blocks in dashed lines cover the case where an additional byte is sent, as described in Section 6.2.1. Fig 5. RTSn functional timing SC68C752B_4 (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 20 January 2010 8 of 48 NXP Semiconductors SC68C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 6.2.2 Auto-CTS The transmitter circuitry checks CTSn before sending the next data byte. When CTSn is active, the transmitter sends the next byte. To stop the transmitter from sending the following byte, CTSn must be de-asserted before the middle of the last stop bit that is currently being sent. The auto-CTS function reduces interrupts to the host system. When flow control is enabled, CTSn level changes do not trigger host interrupts because the device automatically controls its own transmitter. Without auto-CTS, the transmitter sends any data present in the transmit FIFO and a receiver overrun error may result. TXn Start byte 0 to 7 Stop Start byte 0 to 7 Stop CTSn 002aaa227 When CTSn is LOW, the transmitter keeps sending serial data out. When CTSn goes HIGH before the middle of the last stop bit of the current byte, the transmitter finishes sending the current byte, but is does not send the next byte. When CTSn goes from HIGH to LOW, the transmitter begins sending data again. Fig 6. CTSn functional timing 6.3 Software flow control Software flow control is enabled through the Enhanced Feature Register and the Modem Control Register. Different combinations of software flow control can be enabled by setting different combinations of EFR[3:0]. Table 4 shows software flow control options. Table 4. EFR[3] 0 1 0 1 X X X 1 0 1 Software flow control options (EFR[3:0]) EFR[2] 0 0 1 1 X X X 0 1 1 EFR[1] X X X X 0 1 0 1 1 1 EFR[0] X X X X 0 0 1 1 1 1 TX, RX software flow controls no transmit flow control transmit Xon1, Xoff1 transmit Xon2, Xoff2 transmit Xon1, Xon2, Xoff1, Xoff2 no receive flow control receiver compared Xon1, Xoff1 receiver compares Xon2, Xoff2 transmit Xon1, Xoff1 receiver compares Xon1 and Xon2, Xoff1 and Xoff2 transmit Xon2, Xoff2 receiver compares Xon1 and Xon2, Xoff1 and Xoff2 transmit Xon1, Xon2, Xoff1, Xoff2 receiver compares Xon1 and Xon2, Xoff1 and Xoff2 SC68C752B_4 (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 20 January 2010 9 of 48 NXP Semiconductors SC68C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs There are two other enhanced features relating to software flow control: * Xon Any function (MCR[5]): Operation will resume after receiving any character after recognizing the Xoff character. It is possible that an Xon1 character is recognized as an Xon Any character, which could cause an Xon2 character to be written to the RX FIFO. * Special character (EFR[5]): Incoming data is compared to Xoff2. Detection of the special character sets the Xoff interrupt (IIR[4]) but does not halt transmission. The Xoff interrupt is cleared by a read of the IIR. The special character is transferred to the RX FIFO. 6.3.1 Receive flow control When software flow control operation is enabled, the SC68C752B will compare incoming data with Xoff1/Xoff2 programmed characters (in certain cases, Xoff1 and Xoff2 must be received sequentially). When the correct Xoff character are received, transmission is halted after completing transmission of the current character. Xoff detection also sets IIR[4] (if enabled via IER[5]) and causes IRQ to go HIGH. To resume transmission, an Xon1/Xon2 character must be received (in certain cases Xon1 and Xon2 must be received sequentially). When the correct Xon characters are received, IIR[4] is cleared, and the Xoff interrupt disappears. 6.3.2 Transmit flow control Xoff1/Xoff2 character is transmitted when the RX FIFO has passed the HALT trigger level programmed in TCR[3:0]. Xon1/Xon2 character is transmitted when the RX FIFO reaches the RESUME trigger level programmed in TCR[7:4]. The transmission of Xoff/Xon(s) follows the exact same protocol as transmission of an ordinary byte from the FIFO. This means that even if the word length is set to be 5, 6, or 7 characters, then the 5, 6, or 7 least significant bits of Xoff1/Xoff2, Xon1/Xon2 will be transmitted. (Note that the transmission of 5, 6, or 7 bits of a character is seldom done, but this functionality is included to maintain compatibility with earlier designs.) It is assumed that software flow control and hardware flow control will never be enabled simultaneously. Figure 7 shows an example of software flow control. SC68C752B_4 (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 20 January 2010 10 of 48 NXP Semiconductors SC68C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 6.3.3 Software flow control example UART1 UART2 TRANSMIT FIFO RECEIVE FIFO PARALLEL-TO-SERIAL data SERIAL-TO-PARALLEL Xoff-Xon-Xoff SERIAL-TO-PARALLEL PARALLEL-TO-SERIAL Xon1 WORD Xon1 WORD Xon2 WORD Xon2 WORD Xoff1 WORD Xoff1 WORD Xoff2 WORD compare programmed Xon-Xoff characters Xoff2 WORD 002aaa229 Fig 7. Software flow control example 6.3.3.1 Assumptions UART1 is transmitting a large text file to UART2. Both UARTs are using software flow control with single character Xoff (0F) and Xon (0D) tokens. Both have Xoff threshold (TCR[3:0] = F) set to 60, and Xon threshold (TCR[7:4] = 8) set to 32. Both have the interrupt receive threshold (TLR[7:4] = D) set to 52. UART1 begins transmission and sends 52 characters, at which point UART2 will generate an interrupt to its processor to service the RX FIFO, but assume the interrupt latency is fairly long. UART1 will continue sending characters until a total of 60 characters have been sent. At this time, UART2 will transmit a 0Fh to UART1, informing UART1 to halt transmission. UART1 will likely send the 61st character while UART2 is sending the Xoff character. Now UART2 is serviced and the processor reads enough data out of the RX FIFO that the level drops to 32. UART2 will now send a 0Dh to UART1, informing UART1 to resume transmission. SC68C752B_4 (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 20 January 2010 11 of 48 NXP Semiconductors SC68C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 6.4 Reset Table 5 summarizes the state of register after reset. Table 5. Register Interrupt Enable Register Interrupt Identification Register FIFO Control Register Line Control Register Modem Control Register Line Status Register Modem Status Register Enhanced Feature Register Receiver Holding Register Transmitter Holding Register Transmission Control Register Trigger Level Register Register reset functions Reset control RESET RESET RESET RESET RESET RESET RESET RESET RESET RESET RESET RESET Reset state all bits cleared bit 0 is set; all other bits cleared all bits cleared reset to 0001 1101 (1Dh) all bits cleared bits 5 and 6 set; all other bits cleared bits 0 to 3 cleared; bits 4 to 7 input signals all bits cleared pointer logic cleared pointer logic cleared all bits cleared all bits cleared Remark: Registers DLL, DLM, SPR, XON1, XON2, XOFF1, XOFF2 are not reset by the top-level reset signal RESET, that is, they hold their initialization values during reset. Table 6 summarizes the state of registers after reset. Table 6. Signal TXn RTSn DTRn RXRDYn TXRDYn Signal RESET functions Reset control RESET RESET RESET RESET RESET Reset state HIGH HIGH HIGH HIGH LOW SC68C752B_4 (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 20 January 2010 12 of 48 NXP Semiconductors SC68C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 6.5 Interrupts The SC68C752B has interrupt generation and prioritization (six prioritized levels of interrupts) capability. The Interrupt Enable Register (IER) enables each of the six types of interrupts and the IRQ signal in response to an interrupt generation. The IER can also disable the interrupt system by clearing bits 3:0 and bits 7:5. When an interrupt is generated, the IIR indicates that an interrupt is pending and provides the type of interrupt through IIR[5:0]. Table 7 summarizes the interrupt control functions. Table 7. IIR[5:0] 000001 000110 Interrupt control functions Priority Interrupt type level None 1 none receiver line status Interrupt source none OE, FE, PE, or BI errors occur in characters in the RX FIFO Interrupt reset method none FE, PE, BI: all erroneous characters are read from the RX FIFO. OE: read LSR 001100 000100 2 2 RX time-out RHR interrupt stale data in RX FIFO DRDY (data ready) (FIFO disable) RX FIFO above trigger level (FIFO enable) 000010 3 THR interrupt TFE (THR empty) (FIFO disable) TX FIFO passes above trigger level (FIFO enable) 000000 010000 100000 4 5 6 modem status Xoff interrupt CTS, RTS MSR[3:0] = 0 receive Xoff character(s)/ special character RTSn pin or CTSn pin change state from active (LOW) to inactive (HIGH) read MSR receive Xon character(s)/ Read of IIR read IIR read IIR or a write to the THR read RHR read RHR It is important to note that for the framing error, parity error, and break conditions, LSR[7] generates the interrupt. LSR[7] is set when there is an error anywhere in the RX FIFO, and is cleared only when there are no more errors remaining in the FIFO. LSR[4:2] always represent the error status for the received character at the top of the RX FIFO. Reading the RX FIFO updates LSR[4:2] to the appropriate status for the new character at the top of the FIFO. If the RX FIFO is empty, then LSR[4:2] are all zeros. For the Xoff interrupt, if an Xoff flow character detection caused the interrupt, the interrupt is cleared by an Xon flow character detection. If a special character detection caused the interrupt, the interrupt is cleared by a read of the IIR. SC68C752B_4 (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 20 January 2010 13 of 48 NXP Semiconductors SC68C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 6.5.1 Interrupt mode operation In Interrupt mode (if any bit of IER[3:0] is 1) the processor is informed of the status of the receiver and transmitter by an interrupt signal, IRQ. Therefore, it is not necessary to continuously poll the Line Status Register (LSR) to see if any interrupt needs to be serviced. Figure 8 shows Interrupt mode operation. R/W IRQ PROCESSOR IIR IER 1 1 1 1 THR RHR 002aab096 Fig 8. Interrupt mode operation 6.5.2 Polled mode operation In Polled mode (IER[3:0] = 0000) the status of the receiver and transmitter can be checked by polling the Line Status Register (LSR). This mode is an alternative to the FIFO Interrupt mode of operation where the status of the receiver and transmitter is automatically known by means of interrupts sent to the CPU. Figure 9 shows FIFO polled mode operation. R/W PROCESSOR IIR IER 0 0 0 0 THR RHR 002aab097 Fig 9. FIFO polled mode operation SC68C752B_4 (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 20 January 2010 14 of 48 NXP Semiconductors SC68C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 6.6 DMA operation There are two modes of DMA operation, DMA mode 0 or DMA mode 1, selected by FCR[3]. In DMA mode 0 or FIFO disable (FCR[0] = 0) DMA occurs in single character transfers. In DMA mode 1, multi-character (or block) DMA transfers are managed to relieve the processor for longer periods of time. 6.6.1 Single DMA transfers (DMA mode 0/FIFO disable) Figure 10 shows TXRDYn and RXRDYn in DMA mode 0/FIFO disable. transmit receive TXRDYn RXRDYn wrptr at least one location filled rdptr at least one location filled TXRDYn RXRDYn wrptr FIFO EMPTY rdptr FIFO EMPTY 002aaa232 Fig 10. TXRDYn and RXRDYn in DMA mode 0/FIFO disable 6.6.1.1 Transmitter When empty, the TXRDYn signal becomes active. TXRDYn will go inactive after one character has been loaded into it. 6.6.1.2 Receiver RXRDYn is active when there is at least one character in the FIFO. It becomes inactive when the receiver is empty. SC68C752B_4 (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 20 January 2010 15 of 48 NXP Semiconductors SC68C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 6.6.2 Block DMA transfers (DMA mode 1) Figure 11 shows TXRDYn and RXRDYn in DMA mode 1. wrptr transmit trigger level TXRDYn rdptr receive RXRDYn FIFO full trigger level wrptr TXRDYn at least one location filled RXRDYn rdptr FIFO EMPTY 002aaa234 Fig 11. TXRDYn and RXRDYn in DMA mode 1 6.6.2.1 Transmitter TXRDYn is active when there is a trigger level number of spaces available. It becomes inactive when the FIFO is full. 6.6.2.2 Receiver RXRDYn becomes active when the trigger level has been reached, or when a time-out interrupt occurs. It will go inactive when the FIFO is empty or an error in the receive FIFO is flagged by LSR[7]. 6.7 Sleep mode Sleep mode is an enhanced feature of the SC68C752B UART. It is enabled when EFR[4], the enhanced functions bit, is set and when IER[4] is set. Sleep mode is entered when: * The serial data input line, RXn, is idle (see Section 6.8 "Break and time-out conditions"). * The transmit FIFO and transmit shift register are empty. * There are no interrupts pending except THR and time-out interrupts. Remark: Sleep mode will not be entered if there is data in the receive FIFO. In Sleep mode, the UART clock and baud rate clock are stopped. Since most registers are clocked using these clocks, the power consumption is greatly reduced. The UART will wake up when any change is detected on the RXn line, when there is any change in the state of the modem input pins, or if data is written to the transmit FIFO. Remark: Writing to the divisor latches, DLL and DLM, to set the baud clock, must not be done during Sleep mode. Therefore, it is advisable to disable Sleep mode using IER[4] before writing to DLL or DLM. SC68C752B_4 (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 20 January 2010 16 of 48 NXP Semiconductors SC68C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 6.8 Break and time-out conditions An RX idle condition is detected when the receiver line, RXn, has been HIGH for 4 character time. The receiver line is sampled midway through each bit. When a break condition occurs, the TXn line is pulled LOW. A break condition is activated by setting LCR[6]. 6.9 Programmable baud rate generator The SC68C752B UART contains a programmable baud generator that takes any clock input and divides it by a divisor in the range between 1 and (216 - 1). An additional divide-by-4 prescaler is also available and can be selected by MCR[7], as shown in Figure 12. The output frequency of the baud rate generator is 16 times the baud rate. The formula for the divisor is: XTAL1 crystal input frequency ----------------------------------------------------------------------------------- prescaler divisor = ---------------------------------------------------------------------------------------desired baud rate x 16 Where: prescaler = 1, when MCR[7] is set to 0 after reset (divide-by-1 clock selected) prescaler = 4, when MCR[7] is set to 1 after reset (divide-by-4 clock selected). Remark: The default value of prescaler after reset is divide-by-1. Figure 12 shows the internal prescaler and baud rate generator circuitry. (1) PRESCALER LOGIC (DIVIDE-BY-1) XTAL1 XTAL2 INTERNAL OSCILLATOR LOGIC MCR[7] = 0 internal baud rate clock for transmitter and receiver input clock reference clock MCR[7] = 1 BAUD RATE GENERATOR LOGIC PRESCALER LOGIC (DIVIDE-BY-4) 002aaa233 Fig 12. Prescaler and baud rate generator block diagram DLL and DLM must be written to in order to program the baud rate. DLL and DLM are the least significant and most significant byte of the baud rate divisor. If DLL and DLM are both zero, the UART is effectively disabled, as no baud clock will be generated. Remark: The programmable baud rate generator is provided to select both the transmit and receive clock rates. Table 8 and Table 9 show the baud rate and divisor correlation for crystal with frequency 1.8432 MHz and 3.072 MHz, respectively. Figure 13 shows the crystal clock circuit reference. SC68C752B_4 (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 20 January 2010 17 of 48 NXP Semiconductors SC68C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs Baud rates using a 1.8432 MHz crystal Divisor used to generate 16x clock 2304 1536 1047 857 768 384 192 96 64 58 48 32 24 16 12 6 3 2 Baud rates using a 3.072 MHz crystal Divisor used to generate 16x clock 2304 2560 1745 1428 1280 640 320 160 107 96 80 53 40 27 20 10 5 1.23 0.628 0.312 0.026 0.034 Percent error difference between desired and actual 2.86 0.69 0.026 0.058 Percent error difference between desired and actual Table 8. Desired baud rate 50 75 110 134.5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 19200 38400 56000 Table 9. Desired baud rate 50 75 110 134.5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 19200 38400 SC68C752B_4 (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 20 January 2010 18 of 48 NXP Semiconductors SC68C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs XTAL1 XTAL2 XTAL1 XTAL2 1.5 k X1 1.8432 MHz X1 1.8432 MHz C1 22 pF C2 33 pF C1 22 pF C2 47 pF 002aaa870 Fig 13. Crystal oscillator connections 7. Register descriptions Each register is selected using address lines A0, A1, A2, and in some cases, bits from other registers. The programming combinations for register selection are shown in Table 10. Table 10. A2 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 1 1 1 [1] [2] [3] [4] [5] [6] Register map - read/write properties A0 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 1 Read mode Receive Holding Register (RHR) Interrupt Enable Register (IER) Interrupt Identification Register (IIR) Line Control Register (LCR) Modem Control Register (MCR)[1] Line Status Register (LSR) Modem Status Register (MSR) ScratchPad Register (SPR) Divisor Latch LSB (DLL)[2][3] Divisor Latch MSB (DLM)[2][3] Enhanced Feature Register (EFR)[2][4] Xon1 word[2][4] Xon2 word[2][4] Xoff1 word[2][4] Xoff2 word[2][4] Transmission Control Register FIFO ready register[2][6] (TCR)[2][5] Trigger Level Register (TLR)[2][5] ScratchPad Register divisor latch LSB[2][3] divisor latch MSB[2][3] Enhanced Feature Register[2][4] Xon1 word[2][4] Xon2 word[2][4] Xoff1 word[2][4] Xoff2 word[2][4] Transmission Control Register[2][5] Trigger Level Register[2][5] Write mode Transmit Holding Register (THR) Interrupt Enable Register FIFO Control Register (FCR) Line Control Register Modem Control Register[1] A1 0 0 1 1 0 0 1 1 0 0 1 0 0 1 1 1 1 1 MCR[7] can only be modified when EFR[4] is set. Accessed by a combination of address pins and register bits. Accessible only when LCR[7] is logic 1. Accessible only when LCR is set to 1011 1111 (BFh). Accessible only when EFR[4] = 1 and MCR[6] = 1, that is, EFR[4] and MCR[6] are read/write enables. Accessible only when CS = 0, MCR[2] = 1, and loopback is disabled (MCR[4] = 0). SC68C752B_4 (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 20 January 2010 19 of 48 NXP Semiconductors SC68C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs Table 11 lists and describes the SC68C752B internal registers. Table 11. SC68C752B internal registers Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read/ Write R W A2 A1 A0 Register General register set[1] 0 0 0 0 0 0 0 0 1 RHR THR IER bit 7 bit 7 CTS interrupt enable[2] bit 6 bit 6 RTS interrupt enable[2] bit 5 bit 5 Xoff[2] bit 4 bit 4 Sleep mode[2] bit 3 bit 3 modem status interrupt bit 2 bit 2 bit 1 bit 1 bit 0 bit 0 receive THR line status empty interrupt interrupt TX FIFO reset interrupt priority bit 1 RX data R/W available interrupt W 0 1 0 FCR RX trigger RX trigger TX trigger TX trigger DMA level level level level mode (MSB) (LSB) (MSB)[2] (LSB)[2] select FCR[0] FCR[0] CTS, RTS Xoff interrupt priority bit 2 parity enable OPA/ OPB control framing error CD bit 3 bit 3 bit 3 0 RX FIFO FIFO reset enable interrupt priority bit 0 interrupt status word length bit 0 DTR 0 1 0 IIR R 0 1 1 LCR DLAB break set parity parity control bit type select Xon Any[2] THR empty DSR bit 5 bit 5 bit 5 RX FIFO B status bit 5 bit 13 enable loopback break interrupt CTS bit 4 bit 4 bit 4 RX FIFO A status bit 4 bit 12 number of word stop bits length bit 1 FIFO ready enable parity error RI bit 2 bit 2 bit 2 0 RTS R/W 1 0 0 MCR 1x or 1x/4 TCR and clock[2] TLR enable[2] error in RX FIFO CD bit 7 bit 7 bit 7 THR and TSR empty RI bit 6 bit 6 bit 6 0 R/W 1 0 1 LSR overrun error DSR bit 1 bit 1 bit 1 data in receiver CTS bit 0 bit 0 bit 0 R 1 1 1 1 1 1 1 1 1 1 0 1 0 1 1 MSR SPR TCR TLR R R/W R/W R/W R FIFO Rdy 0 TX FIFO TX FIFO B status A status bit 1 bit 9 software flow control bit 1 bit 1 bit 1 bit 1 bit 1 bit 0 bit 8 software flow control bit 0 bit 0 bit 0 bit 0 bit 0 Special register set[3] 0 0 0 0 0 1 0 1 0 DLL DLM EFR bit 7 bit 15 bit 6 bit 14 bit 3 bit 11 bit 2 bit 10 software flow control bit 2 bit 2 bit 2 bit 2 bit 2 R/W R/W R/W Enhanced register set[4] auto-CTS auto-RTS special enable software character enhanced flow detect functions control [2] bit 3 bit 7 bit 7 bit 7 bit 7 bit 6 bit 6 bit 6 bit 6 bit 5 bit 5 bit 5 bit 5 bit 4 bit 4 bit 4 bit 4 bit 3 bit 3 bit 3 bit 3 1 1 1 1 [1] [2] [3] [4] 0 0 1 1 0 1 0 1 XON1 XON2 XOFF1 XOFF2 R/W R/W R/W R/W These registers are accessible only when LCR[7] = 0. This bit can only be modified if register bit EFR[4] is enabled, that is, if enhanced functions are enabled. The Special register set is accessible only when LCR[7] is set to a logic 1. Enhanced Feature Register; XON1/XON2 and XOFF1/XOFF2 are accessible only when LCR is set to `BFh'. (c) NXP B.V. 2010. All rights reserved. SC68C752B_4 Product data sheet Rev. 04 -- 20 January 2010 20 of 48 NXP Semiconductors SC68C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs Remark: Refer to the notes under Table 10 for more register access information. 7.1 Receiver Holding Register (RHR) The receiver section consists of the Receiver Holding Register (RHR) and the Receiver Shift Register (RSR). The RHR is actually a 64-byte FIFO. The RSR receives serial data from the RX terminal. The data is converted to parallel data and moved to the RHR. The receiver section is controlled by the line control register. If the FIFO is disabled, location zero of the FIFO is used to store the characters. Remark: In this case, characters are overwritten if overflow occurs. If overflow occurs, characters are lost. The RHR also stores the error status bits associated with each character. 7.2 Transmit Holding Register (THR) The transmitter section consists of the Transmit Holding Register (THR) and the Transmit Shift Register (TSR). The THR is actually a 64-byte FIFO. The THR receives data and shifts it into the TSR, where it is converted to serial data and moved out on the TX terminal. If the FIFO is disabled, the FIFO is still used to store the byte. Characters are lost if overflow occurs. SC68C752B_4 (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 20 January 2010 21 of 48 NXP Semiconductors SC68C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 7.3 FIFO Control Register (FCR) This is a write-only register that is used for enabling the FIFOs, clearing the FIFOs, setting transmitter and receiver trigger levels, and selecting the type of DMA signalling. Table 12 shows FIFO Control Register bit settings. Table 12. Bit 7:6 FIFO Control Register bits description Description Symbol FCR[7] (MSB), RX trigger. Sets the trigger level for the receive FIFO. FCR[6] (LSB) 00 - 8 characters 01 - 16 characters 10 - 56 characters 11 - 60 characters 5:4 FCR[5] (MSB), TX trigger. Sets the trigger level for the transmit FIFO. FCR[4] (LSB) 00 - 8 spaces 01 - 16 spaces 10 - 32 spaces 11 - 56 spaces FCR[5:4] can only be modified and enabled when EFR[4] is set. This is because the transmit trigger level is regarded as an enhanced function. 3 FCR[3] DMA mode select. logic 0 = Set DMA mode `0' logic 1 = Set DMA mode `1' 2 FCR[2] Reset transmit FIFO. logic 0 = No FIFO transmit reset (normal default condition) logic 1 = Clears the contents of the transmit FIFO and resets the FIFO counter logic (the transmit shift register is not cleared or altered). This bit will return to a logic 0 after clearing the FIFO. 1 FCR[1] Reset receive FIFO. logic 0 = no FIFO receive reset (normal default condition) logic 1 = Clears the contents of the receive FIFO and resets the FIFO counter logic (the receive shift register is not cleared or altered). This bit will return to a logic 0 after clearing the FIFO. 0 FCR[0] FIFO enable. logic 0 = disable the transmit and receive FIFO (normal default condition) logic 1 = enable the transmit and receive FIFO SC68C752B_4 (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 20 January 2010 22 of 48 NXP Semiconductors SC68C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 7.4 Line Control Register (LCR) This register controls the data communication format. The word length, number of stop bits, and parity type are selected by writing the appropriate bits to the LCR. Table 13 shows the Line Control Register bit settings. Table 13. Bit 7 Line Control Register bits description Description Divisor latch enable. logic 0 = divisor latch disabled (normal default condition) logic 1 = divisor latch enabled 6 LCR[6] Break control bit. When enabled, the Break control bit causes a break condition to be transmitted (the TXn output is forced to a logic 0 state). This condition exists until disabled by setting LCR[6] to a logic 0. logic 0 = no break condition (normal default condition) logic 1 = forces the transmitter output (TXn) to a logic 0 to alert the communication terminal to a line break condition 5 LCR[5] Set parity. LCR[5] selects the forced parity format (if LCR[3] = 1). logic 0 = parity is not forced (normal default condition) LCR[5] = logic 1 and LCR[4] = logic 0: parity bit is forced to a logic 1 for the transmit and receive data. LCR[5] = logic 1 and LCR[4] = logic 1: parity bit is forced to a logic 0 for the transmit and receive data. 4 LCR[4] Parity type select. logic 0 = odd parity is generated (if LCR[3] = 1). logic 1 = even parity is generated (if LCR[3] = 1). 3 LCR[3] Parity enable. logic 0 = no parity (normal default condition). logic 1 = a parity bit is generated during transmission and the receiver checks for received parity. 2 LCR[2] Number of stop bits. Specifies the number of stop bits. 0 = 1 stop bit (word length = 5, 6, 7, 8) 1 = 1.5 stop bits (word length = 5) 1 = 2 stop bits (word length = 6, 7, 8) 1:0 LCR[1:0] Word length bits 1, 0. These two bits specify the word length to be transmitted or received. 00 = 5 bits 01 = 6 bits 10 = 7 bits 11 = 8 bits Symbol LCR[7] SC68C752B_4 (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 20 January 2010 23 of 48 NXP Semiconductors SC68C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 7.5 Line Status Register (LSR) Table 14 shows the Line Status Register bit settings. Table 14. Bit 7 Line Status Register bits description Description FIFO data error. logic 0 = No error (normal default condition) logic 1 = At least one parity error, framing error, or break indication is in the receiver FIFO. This bit is cleared when no more errors are present in the FIFO. 6 LSR[6] THR and TSR empty. This bit is the Transmit Empty indicator. logic 0 = transmitter hold and shift registers are not empty logic 1 = transmitter hold and shift registers are empty 5 LSR[5] THR empty. This bit is the Transmit Holding Register Empty indicator. logic 0 = Transmit Hold Register is not empty logic 1 = Transmit Hold Register is empty. The processor can now load up to 64 bytes of data into the THR if the TX FIFO is enabled. 4 LSR[4] Break interrupt. logic 0 = no break condition (normal default condition) logic 1 = A break condition occurred and associated byte is 00, that is, RXn was LOW for one character time frame. 3 LSR[3] Framing error. logic 0 = no framing error in data being read from receive FIFO (normal default condition) logic 1 = Framing error occurred in data being read from receive FIFO, that is, received data did not have a valid stop bit. 2 LSR[2] Parity error. logic 0 = no parity error (normal default condition) logic 1 = parity error in data being read from receive FIFO 1 LSR[1] Overrun error. logic 0 = no overrun error (normal default condition) logic 1 = overrun error has occurred 0 LSR[0] Data in receiver. logic 0 = no data in receive FIFO (normal default condition) logic 1 = at least one character in the receive FIFO Symbol LSR[7] When the LSR is read, LSR[4:2] reflect the error bits (BI, FE, PE) of the character at the top of the receive FIFO (next character to be read). The LSR[4:2] registers do not physically exist, as the data read from the receive FIFO is output directly onto the output data bus, D[4:2], when the LSR is read. Therefore, errors in a character are identified by reading the LSR and then reading the RHR. LSR[7] is set when there is an error anywhere in the receive FIFO, and is cleared only when there are no more errors remaining in the FIFO. Reading the LSR does not cause an increment of the receive FIFO read pointer. The receive FIFO read pointer is incremented by reading the RHR. SC68C752B_4 (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 20 January 2010 24 of 48 NXP Semiconductors SC68C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs Remark: The three error bits (parity, framing, break) may not be updated correctly in the first read of the LSR when the input clock (XTAL1) is running faster than 36 MHz. However, the second read is always correct. It is strongly recommended that when using this device with a clock faster than 36 MHz, that the LSR be read twice and only the second read be used for decision making. All other bits in the LSR are correct on all reads. 7.6 Modem Control Register (MCR) The MCR controls the interface with the mode, data set, or peripheral device that is emulating the modem. Table 15 shows Modem Control Register bit settings. Table 15. Bit 7 Modem Control Register bits description Symbol MCR[7] [1] Description Clock select. logic 0 = divide-by-1 clock input logic 1 = divide-by-4 clock input 6 MCR[6] [1] TCR and TLR enable. logic 0 = no action. logic 1 = enable access to the TCR and TLR registers 5 MCR[5] [1] Xon Any. logic 0 = disable Xon Any function logic 1 = enable Xon Any function 4 MCR[4] Enable loopback. logic 0 = normal operating mode logic 1 = Enable local Loopback mode (internal). In this mode the MCR[3:0] signals are looped back into MSR[7:4] and the TXn output is looped back to the RXn input internally. 3 MCR[3] OPA/OPB control. logic 0 = forces OPA/OPB output to HIGH state logic 1 = forces OPA/OPB output to LOW state. In Loopback mode, controls MSR[7]. 2 MCR[2] FIFO Ready enable. logic 0 = Disable the FIFO Rdy register logic 1 = Enable the FIFO Rdy register. In Loopback mode, controls MSR[6]. 1 MCR[1] RTS logic 0 = force RTSn output to inactive (HIGH) logic 1 = force RTSn output to active (LOW). In Loopback mode, controls MSR[4]. If auto-RTS is enabled, the RTSn output is controlled by hardware flow control. 0 MCR[0] DTR logic 0 = force DTRn output to inactive (HIGH) logic 1 = force DTRn output to active (LOW). In Loopback mode, controls MSR[5]. [1] MCR[7:5] can only be modified when EFR[4] is set, that is, EFR[4] is a write enable. SC68C752B_4 (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 20 January 2010 25 of 48 NXP Semiconductors SC68C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 7.7 Modem Status Register (MSR) This 8-bit register provides information about the current state of the control lines from the mode, data set, or peripheral device to the processor. It also indicates when a control input from the modem changes state. Table 16 shows Modem Status Register bit settings per channel. Table 16. Bit 7 Modem Status Register bits description Description CD (active HIGH, logic 1). This bit is the complement of the CDn input during normal mode. During internal Loopback mode, it is equivalent to the state of MCR[3]. RI (active HIGH, logic 1). This bit is the complement of the RIn input during normal mode. During internal Loopback mode, it is equivalent to the state of MCR[2]. DSR (active HIGH, logic 1). This bit is the complement of the DSRn input during normal mode. During internal Loopback mode, it is equivalent to the state of MCR[0]. CTS (active HIGH, logic 1). This bit is the complement of the CTSn input during normal mode. During internal Loopback mode, it is equivalent to the state of MCR[1]. CD. Indicates that CDn input (or MCR[3] in Loopback mode) has changed state. Cleared on a read. RI. Indicates that RIn input (or MCR[2] in Loopback mode) has changed state from LOW to HIGH. Cleared on a read. DSR. Indicates that DSRn input (or MCR[0] in Loopback mode) has changed state. Cleared on a read. CTS. Indicates that CTSn input (or MCR[1] in Loopback mode) has changed state. Cleared on a read. Symbol MSR[7][1] 6 MSR[6][1] 5 MSR[5][1] 4 MSR[4][1] 3 2 1 0 [1] MSR[3] MSR[2] MSR[1] MSR[0] The primary inputs RIn, CDn, CTSn, DSRn are all active LOW, but their registered equivalents in the MSR and MCR (in Loopback mode) registers are active HIGH. SC68C752B_4 (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 20 January 2010 26 of 48 NXP Semiconductors SC68C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 7.8 Interrupt Enable Register (IER) The Interrupt Enable Register (IER) enables each of the six types of interrupt, receiver error, RHR interrupt, THR interrupt, Xoff received, or CTSn/RTSn change of state from LOW to HIGH. The IRQ output signal is activated in response to interrupt generation. Table 17 shows Interrupt Enable Register bit settings. Table 17. Bit 7 Interrupt Enable Register bits description Description CTS interrupt enable. logic 0 = disable the CTS interrupt (normal default condition) logic 1 = enable the CTS interrupt 6 IER[6][1] RTS interrupt enable. logic 0 = disable the RTS interrupt (normal default condition) logic 1 = enable the RTS interrupt 5 IER[5][1] Xoff interrupt. logic 0 = disable the Xoff interrupt (normal default condition) logic 1 = enable the Xoff interrupt 4 IER[4][1] Sleep mode. logic 0 = disable Sleep mode (normal default condition) logic 1 = enable Sleep mode. See Section 6.7 "Sleep mode" for details. 3 IER[3] Modem Status Interrupt. logic 0 = disable the Modem Status Register interrupt (normal default condition) logic 1 = enable the Modem Status Register interrupt 2 IER[2] Receive Line Status interrupt. logic 0 = disable the receiver line status interrupt (normal default condition) logic 1 = enable the receiver line status interrupt 1 IER[1] Transmit Holding Register interrupt. logic 0 = disable the THR interrupt (normal default condition) logic 1 = enable the THR interrupt 0 IER[0] Receive Holding Register interrupt. logic 0 = disable the RHR interrupt (normal default condition) logic 1 = enable the RHR interrupt [1] IER[7:4] can only be modified if EFR[4] is set, that is, EFR[4] is a write enable. Re-enabling IER[1] will not cause a new interrupt if the THR is below the threshold. Symbol IER[7][1] SC68C752B_4 (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 20 January 2010 27 of 48 NXP Semiconductors SC68C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 7.9 Interrupt Identification Register (IIR) The IIR is a read-only 8-bit register which provides the source of the interrupt in a prioritized manner. Table 18 shows Interrupt Identification Register bit settings. Table 18. Bit 7:6 5 4 3:1 0 Interrupt Identification Register bits description Description Mirror the contents of FCR[0]. RTSn/CTSn LOW-to-HIGH change of state 1 = Xoff/Special character has been detected 3-bit encoded interrupt. See Table 19. Interrupt status. logic 0 = an interrupt is pending logic 1 = no interrupt is pending Symbol IIR[7:6] IIR[5] IIR[4] IIR[3:1] IIR[0] The interrupt priority list is shown in Table 19. Table 19. Priority level 1 2 2 3 4 5 6 Interrupt priority list IIR[5] 0 0 0 0 0 0 1 IIR[4] 0 0 0 0 0 1 0 IIR[3] 0 1 0 0 0 0 0 IIR[2] 1 1 1 0 0 0 0 IIR[1] 1 0 0 1 0 0 0 IIR[0] 0 0 0 0 0 0 0 Source of the interrupt receiver line status error receiver time-out interrupt RHR interrupt THR interrupt modem interrupt received Xoff signal/ special character CTSn, RTSn change of state from active (LOW) to inactive (HIGH) SC68C752B_4 (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 20 January 2010 28 of 48 NXP Semiconductors SC68C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 7.10 Enhanced Feature Register (EFR) This 8-bit register enables or disables the enhanced features of the UART. Table 20 shows the Enhanced Feature Register bit settings. Table 20. Bit 7 Enhanced Feature Register bits description Description CTS flow control enable. logic 0 = CTS flow control is disabled (normal default condition) logic 1 = CTS flow control is enabled. Transmission will stop when a HIGH signal is detected on the CTSn pin. 6 EFR[6] RTS flow control enable. logic 0 = RTS flow control is disabled (normal default condition) logic 1 = RTS flow control is enabled. The RTSn pin goes HIGH when the receiver FIFO halt trigger level TCR[3:0] is reached, and goes LOW when the receiver FIFO resume transmission trigger level TCR[7:4] is reached. 5 EFR[5] Special character detect. logic 0 = special character detect disabled (normal default condition) logic 1 = special character detect enabled. Received data is compared with Xoff2 data. If a match occurs, the received data is transferred to FIFO and IIR[4] is set to a logic 1 to indicate a special character has been detected. 4 EFR[4] Enhanced functions enable bit. logic 0 = disables enhanced functions and writing to IER[7:4], FCR[5:4], MCR[7:5] logic 1 = enables the enhanced function IER[7:4], FCR[5:4], and MCR[7:5] can be modified, that is, this bit is therefore a write enable 3:0 EFR[3:0] Combinations of software flow control can be selected by programming these bits. See Table 4 "Software flow control options (EFR[3:0])" on page 9. Symbol EFR[7] 7.11 Divisor latches (DLL, DLM) These are two 8-bit registers which store the 16-bit divisor for generation of the baud clock in the baud rate generator. DLM stores the most significant part of the divisor. DLL stores the least significant part of the divisor. Note that DLL and DLM can only be written to before Sleep mode is enabled, that is, before IER[4] is set. 7.12 Transmission Control Register (TCR) This 8-bit register is used to store the receive FIFO threshold levels to stop/start transmission during hardware/software flow control. Table 21 shows transmission control register bit settings. Table 21. Bit 7:4 3:0 Transmission Control Register bits description Description receive FIFO trigger level to resume transmission (0 bytes to 60 bytes). receive FIFO trigger level to halt transmission (0 bytes to 60 bytes). Symbol TCR[7:4] TCR[3:0] TCR trigger levels are available from 0 bytes to 60 bytes with a granularity of four. SC68C752B_4 (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 20 January 2010 29 of 48 NXP Semiconductors SC68C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs Remark: TCR can only be written to when EFR[4] = 1 and MCR[6] = 1. The programmer must program the TCR such that TCR[3:0] > TCR[7:4]. There is no built-in hardware check to make sure this condition is met. Also, the TCR must be programmed with this condition before auto-RTS or software flow control is enabled to avoid spurious operation of the device. 7.13 Trigger Level Register (TLR) This 8-bit register is pulsed to store the transmit and received FIFO trigger levels used for DMA and interrupt generation. Trigger levels from 4 to 60 can be programmed with a granularity of 4. Table 22 shows trigger level register bit settings. Table 22. Bit 7:4 3:0 Trigger Level Register bits description Description receive FIFO trigger levels (4 to 60), number of characters available. transmit FIFO trigger levels (4 to 60), number of spaces available. Symbol TLR[7:4] TLR[3:0] Remark: TLR can only be written to when EFR[4] = 1 and MCR[6] = 1. If TLR[3:0] or TLR[7:4] are logic 0, the selectable trigger levels via the FIFO control register (FCR) are used for the transmit and receive FIFO trigger levels. Trigger levels from 4 bytes to 60 bytes are available with a granularity of four. The TLR should be programmed for N4, where N is the desired trigger level. When the trigger level setting in TLR is zero, the SC68C752B uses the trigger level setting defined in FCR. If TLR has non-zero trigger level value, the trigger level defined in FCR is discarded. This applies to both transmit FIFO and receive FIFO trigger level setting. When TLR is used for RX trigger level control, FCR[7:6] should be left at the default state, that is, `00'. 7.14 FIFO ready register The FIFO ready register provides real-time status of the transmit and receive FIFOs of both channels. Table 23. Bit 7:6 5 4 3:2 1 0 FIFO ready register bits description Description unused; always 0 receive FIFO B status; related to DMA receive FIFO A status; related to DMA unused; always 0 transmit FIFO B status; related to DMA transmit FIFO A status; related to DMA Symbol FIFO Rdy[7:6] FIFO Rdy[5] FIFO Rdy[4] FIFO Rdy[3:2] FIFO Rdy[1] FIFO Rdy[0] The FIFO Rdy register is a read-only register that can be accessed when any of the two UARTs is selected CS = 0, MCR[2] (FIFO Rdy Enable) is a logic 1, and loopback is disabled. The address is 111. SC68C752B_4 (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 20 January 2010 30 of 48 NXP Semiconductors SC68C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 8. Programmer's guide The base set of registers that is used during high-speed data transfer have a straightforward access method. The extended function registers require special access bits to be decoded along with the address lines. The following guide will help with programming these registers. Note that the descriptions below are for individual register access. Some streamlining through interleaving can be obtained when programming all the registers. Table 24. Command Set baud rate to VALUE1, VALUE2 Register programming guide Actions read LCR (03h), save in temp set LCR (03h) to 80h set DLL (00h) to VALUE1 set DLM (01h) to VALUE2 set LCR (03h) to temp Set Xoff1, Xon1 to VALUE1, VALUE2 read LCR (03h), save in temp set LCR (03h) to BFh set Xoff1 (06h) to VALUE1 set Xon1 (04h) to VALUE2 set LCR (03h) to temp Set Xoff2, Xon2 to VALUE1, VALUE2 read LCR (03h), save in temp set LCR (03h) to BFh set Xoff2 (07h) to VALUE1 set Xon2 (05h) to VALUE2 set LCR (03h) to temp Set software flow control mode to VALUE read LCR (03h), save in temp set LCR (03h) to BFh set EFR (02h) to VALUE set LCR (03h) to temp Set flow control threshold to VALUE read LCR (03h), save in temp1 set LCR (03h) to BFh read EFR (02h), save in temp2 set EFR (02h) to 10h + temp2 set LCR (03h) to 00h read MCR (04h), save in temp3 set MCR (04h) to 40h + temp3 set TCR (06h) to VALUE set MCR (04h) to temp3 set LCR (03h) to BFh set EFR (02h) to temp2 set LCR (03h) to temp1 SC68C752B_4 (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 20 January 2010 31 of 48 NXP Semiconductors SC68C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs Register programming guide ...continued Actions read LCR (03h), save in temp1 set LCR (03h) to BFh read EFR (02h), save in temp2 set EFR (02h) to 10h + temp2 set LCR (03h) to 00h read MCR (04h), save in temp3 set MCR (04h) to 40h + temp3 set TLR (07h) to VALUE set MCR (04h) to temp3 set LCR (03h) to BFh set EFR (02h) to temp2 set LCR (03h) to temp1 Table 24. Command Set TX FIFO and RX FIFO thresholds to VALUE Read FIFO Rdy register read MCR (04h), save in temp1 set temp2 = temp1 x EFh [1] set MCR (04h) = 40h + temp2 read FFR (07h), save in temp2 pass temp2 back to host set MCR (04h) to temp1 Set prescaler value to divide-by-1 read LCR (03h), save in temp1 set LCR (03h) to BFh read EFR (02h), save in temp2 set EFR (02h) to 10h + temp2 set LCR (03h) to 00h read MCR (04h), save in temp3 set MCR (04h) to temp3 x 7Fh[1] set LCR (03h) to BFh set EFR (02h) to temp2 set LCR (03h) to temp1 Set prescaler value to divide-by-4 read LCR (03h), save in temp1 set LCR (03h) to BFh read EFR (02h), save in temp2 set EFR (02h) to 10h + temp2 set LCR (03h) to 00h read MCR (04h), save in temp3 set MCR (04h) to temp3 + 80h set LCR (03h) to BFh set EFR (02h) to temp2 set LCR (03h) to temp1 [1] x sign here means bit-AND. SC68C752B_4 (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 20 January 2010 32 of 48 NXP Semiconductors SC68C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 9. Limiting values Table 25. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VCC Vn VO Tamb Tstg Parameter supply voltage voltage on any other pin at D7 to D0 at any input only pin output voltage ambient temperature storage temperature operating in free-air Conditions Min GND - 0.3 GND - 0.3 -0.3 -40 -65 Max 7 VCC + 0.3 5.3 VCC + 0.3 +85 +150 Unit V V V V C C SC68C752B_4 (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 20 January 2010 33 of 48 NXP Semiconductors SC68C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 10. Static characteristics Table 26. Static characteristics Tolerance of VCC = 10 %. Symbol Parameter VCC VI VIH VIL VO VOH supply voltage input voltage HIGH-level input voltage LOW-level input voltage output voltage HIGH-level output voltage IOH = -8 mA IOH = -4 mA IOH = -800 A IOH = -400 A VOL LOW-level output voltage IOL = 8 mA IOL = 4 mA IOL = 2 mA IOL = 1.6 mA Ci Tamb Tj fXTAL1 ICC input capacitance ambient temperature junction temperature frequency on pin XTAL1 clock duty cycle supply current f = 5 MHz [8] [1] Conditions Min VCC = 2.5 V Typ VCC +25 +25 50 Max VCC VCC 0.65 VCC 0.4 0.4 18 +85 +125 50 3.5 200 VCC - 10 % 0 1.6 0 1.85 1.85 - VCC = 3.3 V and 5 V Min 0 2.0 0 2.0 2.0 -40 0 Typ VCC +25 +25 50 Max Unit VCC + 10 % VCC - 10 % VCC + 10 % V VCC VCC 0.8 VCC 0.4 0.4 18 +85 +125 80 4.5 200 V V V V V V V V V V V V pF C C MHz % mA A [1] [2] [3] [4] [3] [4] [3][5] [4][5] [3][5] [4][5] operating [6] -40 0 - [7] ICC(sleep) sleep mode supply current [1] [2] [3] [4] [5] [6] [7] [8] Meets TTL levels, VIL(min) = 2 V and VIH(max) = 0.8 V on non-hysteresis inputs. Applies for external output buffers. These parameters apply for D[7:0]. These parameters apply for DTRA, DTRB, RTSA, RTSB, RXRDYA, RXRDYB, TXRDYA, TXRDYB, TXA, TXB. Except XTAL2, VOL = 1 V typical. These junction temperatures reflect simulated conditions. Absolute maximum junction temperature is 150 C. The customer is responsible for verifying junction temperature. Applies to external clock; crystal oscillator max. 24 MHz. Measurement condition, normal operation other than Sleep mode: VCC = 3.3 V; Tamb = 25 C. Full duplex serial activity on all two serial (UART) channels at the clock frequency specified in the recommended operating conditions with divisor of 1. SC68C752B_4 (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 20 January 2010 34 of 48 NXP Semiconductors SC68C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 11. Dynamic characteristics Table 27. Dynamic characteristics Tamb = -40 C to +85 C; tolerance of VCC 10 %, unless specified otherwise. Symbol td1 td2 td3 td4 td6 td7 td8 td9 td10 td11 td12 td13 td14 td15 td16 td17 td18 th2 th3 th4 tWL tWH fXTAL1 t(RESET) tsu1 tsu2 tw1 [1] [2] [3] [4] Parameter R/W to chip select read cycle delay delay from CS to data data disable time write cycle delay delay from WRITE to output delay to set interrupt from modem input delay to reset interrupt from READ delay from stop to set interrupt delay from READ to reset interrupt delay from start to set interrupt delay from WRITE to transmit start delay from WRITE to reset interrupt delay from stop to set RXRDY delay from READ to reset RXRDY delay from WRITE to set TXRDY delay from start to reset TXRDY R/W hold time from CS data hold time address hold time pulse width LOW pulse width HIGH frequency on pin XTAL1 RESET pulse width address setup time data setup time CS strobe width Conditions VCC = 2.5 V Min 10 Max 77 15 100 100 100 1TRCLK[1] 100 100 [1] VCC = 3.3 V and 5 V Min 10 20 25 [1] Unit ns ns ns ns ns ns ns ns s ns ns Max 26 15 33 24 24 1TRCLK[1] 29 100 [1] 25 pF load 25 pF load 25 pF load 25 pF load 25 pF load 25 pF load 25 pF load 20 25 8TRCLK 10 15 15 10 10 [2][3] [4] 24TRCLK 100 8TRCLK 10 15 15 6 6 200 10 16 30 24TRCLK 70 [1] s ns s ns ns ns ns ns ns ns MHz ns ns ns ns 1TRCLK[1] 100 100 16TRCLK[1] 48 - 1TRCLK[1] 75 70 80 - 16TRCLK[1] s 200 10 16 77 RCLK is an internal signal derived from Divisor Latch LSB (DLL) and Divisor Latch MSB (DLM) divisor latches. Applies to external clock; crystal oscillator max 24 MHz. Maximum frequency = -------------Reset pulse must occur when CS is inactive. 1 t w ( clk ) SC68C752B_4 (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 20 January 2010 35 of 48 NXP Semiconductors SC68C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 11.1 Timing diagrams A0 to A3 tsu1 CS td1 valid address tw1 th4 valid address td2 td4 R/W td3 D0 to D7 valid data valid data 002aab087 Fig 14. General read timing A0 to A3 tsu1 valid address tw1 th4 valid address CS td1 th2 td6 R/W tsu2 th3 D0 to D7 valid data valid data 002aab088 Fig 15. General write timing SC68C752B_4 (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 20 January 2010 36 of 48 NXP Semiconductors SC68C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs CS (write)(1) active td7 RTSA, RTSB DTRA, DTRB change of state change of state CDA, CDB CTSA, CTSB DSRA, DSRB td8 change of state td8 change of state IRQ active td9 active active CS (read)(2) active active td8 active RIA, RIB change of state 002aab089 (1) CS timing during a write cycle. See Figure 15. (2) CS timing during a read cycle. See Figure 14. Fig 16. Modem input/output timing tWL external clock tWH tw(clk) 002aac357 1 f XTAL1 = -------------t w ( clk ) Fig 17. External clock timing SC68C752B_4 (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 20 January 2010 37 of 48 NXP Semiconductors SC68C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs Start bit data bits (0 to 7) D0 D1 D2 5 data bits 6 data bits 7 data bits D3 D4 D5 D6 D7 parity bit Stop bit next data Start bit RXA, RXB td10 active td11 IRQ CS (read) active 16 baud rate clock 002aab090 Fig 18. Receive timing Start bit data bits (0 to 7) D0 D1 D2 D3 D4 D5 D6 D7 parity bit Stop bit next data Start bit RXA, RXB td15 RXRDYA, RXRDYB active data ready td16 CS (read) active 002aab091 Fig 19. Receive ready timing in non-FIFO mode SC68C752B_4 (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 20 January 2010 38 of 48 NXP Semiconductors SC68C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs Start bit data bits (0 to 7) D0 D1 D2 D3 D4 D5 D6 D7 parity bit Stop bit RXA, RXB first byte that reaches the trigger level td15 RXRDYA, RXRDYB active data ready td16 CS (read) active 002aab092 Fig 20. Receive ready timing in FIFO mode Start bit data bits (0 to 7) D0 D1 D2 5 data bits 6 data bits 7 data bits active transmitter ready D3 D4 D5 D6 D7 parity bit Stop bit next data Start bit TXA, TXB IRQ td12 td13 td14 active CS (write) active 16 baud rate clock 002aab093 Fig 21. Transmit timing SC68C752B_4 (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 20 January 2010 39 of 48 NXP Semiconductors SC68C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs Start bit TXA, TXB data bits (0 to 7) D0 D1 D2 D3 D4 D5 D6 D7 parity bit Stop bit next data Start bit CS (write) active D0 to D7 byte #1 td18 td17 TXRDYA, TXRDYB active transmitter ready transmitter not ready 002aab094 Fig 22. Transmit ready timing in non-FIFO mode start bit data bits (0 to 7) D0 D1 D2 D3 D4 D5 D6 D7 parity bit stop bit TXA, TXB 5 data bits 6 data bits 7 data bits CS (write) active td18 D0 to D7 byte #64 td17 TXRDYA, TXRDYB trigger lead 002aab377 Fig 23. Transmit ready timing in FIFO mode SC68C752B_4 (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 20 January 2010 40 of 48 NXP Semiconductors SC68C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 12. Package outline LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2 c y X 36 37 25 24 ZE A e E HE A A2 A1 (A 3) Lp L detail X wM pin 1 index 48 1 12 ZD bp D HD wM B vM B vM A 13 bp e 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.20 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.18 0.12 D (1) 7.1 6.9 E (1) 7.1 6.9 e 0.5 HD 9.15 8.85 HE 9.15 8.85 L 1 Lp 0.75 0.45 v 0.2 w 0.12 y 0.1 Z D (1) Z E (1) 0.95 0.55 0.95 0.55 7 o 0 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT313-2 REFERENCES IEC 136E05 JEDEC MS-026 JEITA EUROPEAN PROJECTION ISSUE DATE 00-01-19 03-02-25 Fig 24. Package outline SOT313-2 (LQFP48) SC68C752B_4 (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 20 January 2010 41 of 48 NXP Semiconductors SC68C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs HVQFN32: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 x 5 x 0.85 mm SOT617-1 D B A terminal 1 index area E A A1 c detail X e1 e 9 L 8 17 e 1/2 C eb 16 vMCAB wMC y1 C y Eh 1/2 e2 e 1 terminal 1 index area 24 32 Dh 0 2.5 scale E (1) 5.1 4.9 Eh 3.25 2.95 e 0.5 e1 3.5 e2 3.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1 5 mm 25 X DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 5.1 4.9 Dh 3.25 2.95 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT617-1 REFERENCES IEC --JEDEC MO-220 JEITA --EUROPEAN PROJECTION ISSUE DATE 01-08-08 02-10-18 Fig 25. Package outline SOT617-1 (HVQFN32) SC68C752B_4 (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 20 January 2010 42 of 48 NXP Semiconductors SC68C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 13. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description". 13.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 13.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: * Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: * * * * * * Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 13.3 Wave soldering Key characteristics in wave soldering are: * Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave * Solder bath specifications, including temperature and impurities SC68C752B_4 (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 20 January 2010 43 of 48 NXP Semiconductors SC68C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 13.4 Reflow soldering Key characteristics in reflow soldering are: * Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 26) than a SnPb process, thus reducing the process window * Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board * Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 28 and 29 Table 28. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 29. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220 Package thickness (mm) Package thickness (mm) Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 26. SC68C752B_4 (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 20 January 2010 44 of 48 NXP Semiconductors SC68C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 26. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description". 14. Abbreviations Table 30. Acronym CPU DMA FIFO LSB MSB PCB TTL UART Abbreviations Description Central Processing Unit Direct Memory Access First In/First Out Least Significant Bit Most Significant Bit Printed-Circuit Board Transistor-Transistor Logic Universal Asynchronous Receiver and Transmitter SC68C752B_4 (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 20 January 2010 45 of 48 NXP Semiconductors SC68C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 15. Revision history Table 31. Revision history Release date 20100120 Data sheet status Product data sheet Change notice Supersedes SC68C752B_3 Document ID SC68C752B_4 Modifications: * * * * The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Descriptive title of data sheet modified: changed from "Motorola" to "68 mode" Section 2 "Features": - 1st bullet item changed from "Motorola P interface" to "68 mode (Motorola) P interface" - 10th bullet item changed from "5 V tolerant inputs" to "5 V tolerant on input only pins" - 10th bullet item added Footnote 1 * * * Table 2 "Pin description": added Table note [1] and its reference at HVQFN32 pin 13. Section 7.11 "Divisor latches (DLL, DLM)": changed from "DLH" to "DLM" (and throughout data sheet) Table 25 "Limiting values": - removed specification for VI - added specification for Vn - removed table note [1] and its reference (statement is now covered in Section 16.3) * * Table 26 "Static characteristics": parameter for ICC(sleep) changed from "sleep current" to "sleep mode supply current" Table 27 "Dynamic characteristics": - added Table note [4] and its reference at t(RESET) - split symbol/parameter "tw1, tw2, clock cycle period" to two symbol/parameters, "tWH, pulse width HIGH" and "tWL, pulse width LOW" - denominator in equation in Table note [3] changed from "tw3" to "tw(clk)" * Figure 17 "External clock timing": - changed symbol from "tw1" to "tWH" - changed symbol from "tw2" to "tWL" - changed symbol from "tw3" to "tw(clk)" (in both drawing and equation denominator) SC68C752B_3 SC68C752B_2 (9397 750 14963) SC68C752B_1 (9397 750 13857) 20051129 20050428 20050329 Product data sheet Product data sheet Product data sheet - SC68C752B_2 SC68C752B_1 - SC68C752B_4 (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 20 January 2010 46 of 48 NXP Semiconductors SC68C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 16. Legal information 16.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 16.3 Disclaimers General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com SC68C752B_4 (c) NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 -- 20 January 2010 47 of 48 NXP Semiconductors SC68C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs 18. Contents 1 2 3 4 5 5.1 5.2 6 6.1 6.2 6.2.1 6.2.2 6.3 6.3.1 6.3.2 6.3.3 6.3.3.1 6.4 6.5 6.5.1 6.5.2 6.6 6.6.1 6.6.1.1 6.6.1.2 6.6.2 6.6.2.1 6.6.2.2 6.7 6.8 6.9 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 7 Trigger levels . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Hardware flow control . . . . . . . . . . . . . . . . . . . . 7 Auto-RTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Auto-CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Software flow control . . . . . . . . . . . . . . . . . . . . 9 Receive flow control . . . . . . . . . . . . . . . . . . . . 10 Transmit flow control. . . . . . . . . . . . . . . . . . . . 10 Software flow control example . . . . . . . . . . . . 11 Assumptions . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Interrupt mode operation . . . . . . . . . . . . . . . . 14 Polled mode operation . . . . . . . . . . . . . . . . . . 14 DMA operation . . . . . . . . . . . . . . . . . . . . . . . . 15 Single DMA transfers (DMA mode 0/FIFO disable). . . . . . . . . . . . . . 15 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Block DMA transfers (DMA mode 1). . . . . . . . 16 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Break and time-out conditions . . . . . . . . . . . . 17 Programmable baud rate generator . . . . . . . . 17 Register descriptions . . . . . . . . . . . . . . . . . . . 19 Receiver Holding Register (RHR). . . . . . . . . . 21 Transmit Holding Register (THR) . . . . . . . . . . 21 FIFO Control Register (FCR) . . . . . . . . . . . . . 22 Line Control Register (LCR) . . . . . . . . . . . . . . 23 Line Status Register (LSR) . . . . . . . . . . . . . . . 24 Modem Control Register (MCR) . . . . . . . . . . . 25 Modem Status Register (MSR) . . . . . . . . . . . . 26 Interrupt Enable Register (IER) . . . . . . . . . . . 27 Interrupt Identification Register (IIR). . . . . . . . 28 Enhanced Feature Register (EFR) . . . . . . . . . 29 Divisor latches (DLL, DLM). . . . . . . . . . . . . . . 29 Transmission Control Register (TCR). . . . . . . 29 Trigger Level Register (TLR) . . . . . . . . . . . . . 30 FIFO ready register . . . . . . . . . . . . . . . . . . . . 30 8 9 10 11 11.1 12 13 13.1 13.2 13.3 13.4 14 15 16 16.1 16.2 16.3 16.4 17 18 Programmer's guide . . . . . . . . . . . . . . . . . . . . Limiting values . . . . . . . . . . . . . . . . . . . . . . . . Static characteristics . . . . . . . . . . . . . . . . . . . Dynamic characteristics. . . . . . . . . . . . . . . . . Timing diagrams. . . . . . . . . . . . . . . . . . . . . . . Package outline. . . . . . . . . . . . . . . . . . . . . . . . Soldering of SMD packages . . . . . . . . . . . . . . Introduction to soldering. . . . . . . . . . . . . . . . . Wave and reflow soldering. . . . . . . . . . . . . . . Wave soldering . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 33 34 35 36 41 43 43 43 43 44 45 46 47 47 47 47 47 47 48 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'. (c) NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 20 January 2010 Document identifier: SC68C752B_4 |
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